Year: 2024
Type: article
Abstract: In today's tech-driven landscape, semiconductor chips are critical to the functionality of most modern devices, requiring compact designs and low power consumption for efficient data storage and memory. SRAM (Static Random Access Memory) is key to meeting these demands. This study leverages Cadence Virtuoso software to design a high-performance sense amplifier circuit specifically tailored for low-power SRAM applications. Various power reduction strategies were explored, resulting in an optimized solution within a redesigned SRAM architecture. The study analyzes the impact of power consumption and response time of the proposed sense amplifier by adjusting key parameters, such as the transistor width-to-length (W/L) ratio, power supply, and nanoscale technology. Detailed metrics on power usage and transistor count for different configurations are presented to identify the most effective approach. Our proposed low-power sense amplifier design shows promising results, incorporating three VLSI power reduction techniques to enhance efficiency. These innovations in low-power SRAM are poised to advance memory-centric neuromorphic computing applications.
Source: Nanotechnology Perceptions
Authors: Km. Ankita Kumari Singh, Vishal Yadav, Ajay Kumar Maurya, Ravi Prakash
Institution: Veer Bahadur Singh Purvanchal University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4405233303