Work

Nanowire junctionless ISFET noise model in Verilog-A

Year: 2024

Type: article

Abstract: In this paper, we validate the Verilog-A implementation of the nanowire ISFET model. Based on the developed code and EKV formalism, the flicker noise of the nanowire ISFET was studied. The Verilog-A code was validated by comparing the data obtained from the circuit simulator with corresponding data from COMSOL simulations. The good agreement between these simulations demonstrates the accuracy of the code and readout circuit. This noise analysis predicts the dependence of nanowire ISFET flicker noise on different system parameters. This approach is dedicated to assist designers in optimising the device before its implementation.

Source: International Journal of Electronics Letters

DOI: 10.1080/21681724.2024.2437361

Authors: Narek Yezakyan, Ashkhen Yesayan, Jean-Michel Sallese

Institutions: Institute of Radiophysics and Electronics, Yerevan State University, École Polytechnique Fédérale de Lausanne

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

Funder: State Committee of Science

OpenAlex ID: W4405260324

FWCI:

Cites: 19

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Related to: 10