Design of hardware accelerator for target recognition convolutional neural network based on DSP+FPGA architecture
Year: 2024
Type: conference-paper
DOI: 10.1117/12.3045653
Authors: Bocheng Lu, Chuangang Xu, Shiliang Li, Ping Sun, Jingfeng Zhang
Language: English
Subfield: Computer Vision and Pattern Recognition
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4405362869