Work

Mitigation of 1-Row Hammer in BCAT Structures Through Buried Oxide Integration and Investigation of Inter-Cell Disturbances

Year: 2024

Type: article

Abstract: Dynamic random-access memory (DRAM) is crucial for high-performance computing due to its speed and storage capacity. As the demand for high-capacity memory increases, DRAM has adopted a scaled-down approach for the next generation. However, the reduced distance between cells leads to electrical interference, known as the 1-row Hammer effect, which degrades DRAM performance and poses security risks. Therefore, the 1-row Hammer effect is a critical issue in current DRAM technology. In this study, we investigate the principles and impact of the 1-row Hammer phenomenon on DRAM. The 1-row Hammer effect can cause two types of failures: D0 and D1. We focus on D0 failures, which occur when stored data transition from 0 to 1 due to repeated accesses. This phenomenon involves the capture and diffusion of electrons, influenced by interfacial traps and device structures. To investigate the D0 failure, we simulated the 1-row Hammer effect using a mixed-mode approach to examine its effects on interfacial traps and device structure changes. This study aims to improve our understanding of row Hammer and suggests a mitigation strategy using buried oxide. The proposed structure mitigates the D0 failure by approximately 25%, effectively improving the security and reliability of DRAM.

Source: Electronics

DOI: 10.3390/electronics13244936

Authors: Yeon-Seok Kim, Min-Woo Kwon

Institutions: Gangneung–Wonju National University, Seoul National University of Science and Technology

Language: English

Topic: Semiconductor materials and devices

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $2,728