Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells
Year: 2024
Type: article
Abstract: Modern processors experience memory contention when the speed of their computational units exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory wall and is a great challenge in computer engineering. The reason for this phenomenon is the unequal growth rate in memory access speeds compared to processor clock rates. To mitigate the memory bottleneck in classic computer architectures, a scalable parallel computing platform—the Grid of Processing Cells (GPC)—has been proposed. To evaluate its effectiveness, the GPC is modeled at the instruction level and functional level using SystemC TLM-2.0, with a focus on memory contention. Individual GPC cells can be switched between the two abstraction levels. Our mixed-level system model enables fast and accurate simulations. We test multiple streaming applications on the GPC, and analyze software-based optimization methods and their effects on the GPC, at both abstraction levels. The performance is then compared against the traditional shared memory processor architecture. Experimental results show improved execution times on the GPC primarily due to a large decrease in main memory contention.
DOI: 10.1145/3708988
Authors: Vivek Govindasamy, Rainer Doemer
Institution: University of California, Irvine
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4405578731