Work

TSPC STC-DET Flip-Flop With Autogated Clock Gating For Low-Power

Year: 2024

Type: conference-paper

Source: International Conference on Electronics, Communication and Aerospace Technology (ICECA)

DOI: 10.1109/iceca63461.2024.10800954

Authors: Nazir Nadaf, Sonali Agrawal

Institution: Amrita Vishwa Vidyapeetham

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4405755537

FWCI: 1.611

Cites: 10

Cited by: 2

Related to: 10