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A Novel Three-Stage CTLE Circuit for 12.5Gbps SerDes

Year: 2024

Type: conference-paper

Source: International Conference on Electronic Information Engineering and Computer Science (EIECS)

DOI: 10.1109/eiecs63941.2024.10800491

Authors: Zuohan Yang, Lei Chen, Jian Zhang, Maoxin Chen, Zuhang Wang, Yidong Cao

Institution: Beijing Microelectronics Technology Institute

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4405755592

FWCI:

Cites: 12

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Related to: 10