Work

Developing a digital twin to measure and optimise HPC efficiency

Year: 2024

Type: article

Abstract: A Digital Twin for a high-performance computer requires the integration of many sensors and data sources for monitoring operation and tuning of the system. This paper introduces the network concept for the Digital Twin of PTB's HPC cluster with agents, software components to collect, process and send measurement data to the database of the Digital Twin, and how sensors are separated into networks for security of the data centre. The Digital Twin is used to tune the system for reduced CO 2 emissions. In a first step, the focus lies on two control parameters: Processor frequencies, scaled specifically to maximise energy savings, and a modified scheduling mechanism, with deliberate delays helping to exploit phases of low CO 2 emissions. In the simulation, frequency scaling showed saving of 3–4 percent and the modified scheduling mechanism, depending on the workload, of 1–9 percent. Combining both methods allowed for savings of up to 11 percent.

Source: Measurement Sensors

DOI: 10.1016/j.measen.2024.101481

Authors: Alexander Kammeyer, Florian Burger, Daniel Lübbert, Katinka Wolter

Institutions: Physikalisch-Technische Bundesanstalt, Freie Universität Berlin

Language: English

Topic: Energy Efficiency in Computing

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDGs: Industry, innovation and infrastructure, Climate action

Open Access status: gold

Estimated APC paid: $1,800