Work

Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques

Year: 2024

Type: conference-paper

Source: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

DOI: 10.1109/apccas62602.2024.10808655

Authors: Chen-Ho Chen, Chien-Nan Jimmy Liu, Wei-Ting Tu, Tung-Chieh Chen, Iris Hui-Ru Jiang

Institutions: National Yang Ming Chiao Tung University, National Taiwan University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4405845162

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Cites: 20

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Related to: 10