Multiple-Loop Analysis and Design for Fast-Transient Capacitor-less LDO with Dual-Path Compensation and Zero-Pole placement in 65-nm CMOS
Year: 2024
Type: conference-paper
Authors: Peijuan Ju, Qisong Wu, Dixian Zhao
Institution: Southeast University
Language: English
Subfield: Biomedical Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4405845907