Work

A Stochastic RMS Jitter Monitoring Circuit for Clock Generators using Central Limit Theorem

Year: 2024

Type: conference-paper

Source: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

DOI: 10.1109/apccas62602.2024.10808607

Authors: Hyeonmin Park, Ahryung Kim, Jeyeon Lee, SeongHwan Cho

Institution: Korea Advanced Institute of Science and Technology

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4405846022

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Cites: 9

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Related to: 10