Work

A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering

Year: 2024

Type: article

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2024.3513435

Authors: Ke Li, Haoyu Gong, Congzhou Xianyu, Zhensheng Li, Liang Qi, Mingqiang Guo, Rui P. Martins, Sai-Weng Sin

Institutions: University of Macau, Shanghai Jiao Tong University

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: Science and Technology Development Fund, Universidade de Macau, National Key Research and Development Program of China

Awards: G4678931487, G6583377296, G7916285504, G8009088012

OpenAlex ID: W4405846502

FWCI: 0.842

Cites: 35

Cited by: 8

Related to: 10