Work

In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection

Year: 2024

Type: conference-paper

Source: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

DOI: 10.1109/apccas62602.2024.10808985

Authors: Jinn-Shyan Wang, Yong-Chin Miu, Chia-Hua Wu

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: National Science and Technology Council

OpenAlex ID: W4405846670

FWCI: 2.418

Cites: 12

Cited by: 3

Related to: 10