Work

A 2.5Gb/s CDR-PLL with Improved Phase Detector for Jitter Tolerance Enhancement

Year: 2024

Type: conference-paper

Source: IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)

DOI: 10.1109/imfedk64776.2024.10814339

Authors: Yasuhiro Okada, Tsutomu Yoshimura

Institution: Osaka Institute of Technology

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4405907241

FWCI:

Cites: 3

Cited by:

Related to: 10