Work

LlamaF: An Efficient Llama2 Architecture Accelerator on Embedded FPGAs

Year: 2024

Type: conference-paper

Abstract: Large language models (LLMs) have demonstrated remarkable abilities in natural language processing. However, their deployment on resource-constrained embedded devices remains difficult due to memory and computational demands. In this paper, we present an FPGA-based accelerator designed to improve LLM inference performance on embedded FPGAs. We employ post-training quantization to reduce model size and optimize for off-chip memory bandwidth. Our design features asynchronous computation and a fully pipelined accelerator for matrix-vector multiplication. Experiments of the TinyLlama 1.1B model on a Xilinx ZCU102 platform show a 14.3-15.8x speedup and a 6.1x power efficiency improvement over running exclusively on ZCU102 processing system (PS).

Source: IEEE World Forum on Internet of Things (WF-IoT)

DOI: 10.1109/wf-iot62078.2024.10811385

Authors: Han Xu, Yutong Li, Shihao Ji

Institutions: University of Illinois Urbana-Champaign, Georgia State University

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green

Funder: VMware