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A Five-Stage Pipelined Processor Circuit Design Based on RISC-V

Year: 2024

Type: conference-paper

Source: International Conference on Integrated Circuits and Microsystems (ICICM)

DOI: 10.1109/icicm63644.2024.10814430

Authors: Jiucun Pan, Dingze Lu, Zhiguo Xue, Jing Li, Zhanghai You, Hang He

Institutions: Xi'an Polytechnic University, Xi’an University of Posts and Telecommunications

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4405936609

FWCI:

Cites: 11

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Related to: 10