Work

Static Timing Analysis of Modified 8 Bit Pipelined Multiplier with Carry Lookahead Adder Approach

Year: 2024

Type: conference-paper

DOI: 10.1109/csitss64042.2024.10816828

Authors: Revanna J T, Gurudatt B M, G R Deepakkumar, Vedashree B S, Shylashree N

Institution: R.V. College of Engineering

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4405974445

FWCI: 0.806

Cites: 15

Cited by: 1

Related to: 10