Work

Design and Simulation of CMOS Fractional-N All-Digital Phase-Locked Loop (ADPLL)

Year: 2024

Type: conference-paper

DOI: 10.1109/imas61316.2024.10818114

Author: Tangus Koech

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4405974530

FWCI: 0.806

Cites: 4

Cited by: 1

Related to: 10