Work

Design and Timing Analysis of 32 Bit Floating Point Pipelined Multiplier

Year: 2024

Type: conference-paper

DOI: 10.1109/csitss64042.2024.10816738

Authors: Surabhi A S, Amogh Yogesh Naragund, Sahana M S, Keerthana V, Shylashree N

Institution: R.V. College of Engineering

Language: English

Topic: Numerical Methods and Algorithms

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4405975470

FWCI:

Cites: 14

Cited by:

Related to: 10