Work

Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology

Year: 2024

Type: conference-paper

Source: International Conference on Contemporary Computing and Informatics (IC3I)

DOI: 10.1109/ic3i61595.2024.10828606

Authors: Sanjeev Kumar, Kanika Jindal, Pavan Kumar Shukla

Institution: Noida Institute of Engineering and Technology

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4406416477

FWCI: 2.418

Cites:

Cited by: 3

Related to: 10