Work

Stream-HLS: Towards Automatic Dataflow Acceleration

Year: 2025

Type: conference-paper

Abstract: High-level synthesis (HLS) has enabled the rapid development of custom hardware circuits for many software applications. However, developing high-performance hardware circuits using HLS is still a non-trivial task requiring expertise in hardware design. Further, the hardware design space, especially for multi-kernel applications, grows exponentially. Therefore, several HLS automation and abstraction frameworks have been proposed recently, but many issues remain unresolved. These issues include: 1) relying mainly on hardware directives (pragmas) to apply hardware optimizations without exploring loop scheduling opportunities. 2) targeting single-kernel applications only. 3) lacking automatic and/or global design space exploration. 4) missing critical hardware optimizations, such as graph-level pipelining for multi-kernel applications.

Source: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

DOI: 10.1145/3706628.3708878

Authors: Suhail Basalama, Jason Cong

Institution: University of California, Los Angeles

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Funders: National Science Foundation, Semiconductor Research Corporation

Awards: RTML: Large: Acceleration to Graph-Based Machine Learning, SHF: Medium: Automating High Level Synthesis via Graph-Centric Deep Learning