Work

Up to 60% More Linear Area Efficient Asymmetric 6T (6TA) SRAM Cell for In-Memory Compute

Year: 2024

Type: conference-paper

Source: IEEE International Conference on Electronics, Circuits and Systems (ICECS)

DOI: 10.1109/icecs61496.2024.10848731

Authors: Ajay Shroti, Anuj Grover

Institution: Indian Institute of Technology Delhi

Language: English

Topic: Advanced Memory and Neural Computing

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4406894841

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