Year: 2024
Type: conference-paper
Abstract: This paper presents a comprehensive verification environment and methodology for fully verifying a System on Chip-Field-Programmable Gate Array (SoC-FPGA) used in building an NQR spectrometer through RTL simulation. The verification environment includes an RTL testbench, a database of tests, design modules simulation models, and simulation automation scripts. Initially, the system is simulated in an RTL testbench written in System Verilog, with the SoC-FPGA as the Device Under Test (DUT). To simulate real NMR/NQR experiments, various tests are created, each corresponding to a specific experiment, comprising stimuli, current test configuration files and reference files. For each test, the simulation output files of the DUT are compared bit-wise to the reference files. Simulation and check scripts provide a snapshot of the design's non-regression status. This methodology and platform enable in-depth verification of the SoC-FPGA's functionality, significantly reducing the experimental validation time of the NQR spectrometer on real samples. Future enhancements could include verifying the signal denoising algorithms implemented on the SoC-FPGA.
Authors: Nor Eddine Kachkachi, Hassan Rabah
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4406894979