Work

A 45-fs rms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology

Year: 2024

Type: conference-paper

Source: IEEE Asian Solid-State Circuits Conference (A-SSCC)

DOI: 10.1109/a-sscc60305.2024.10849120

Authors: Subhadeep Datta, Arnab Banerjee, Ayush Tripathi, Dongmin Kang, Sunghyuck Lee, Hasung Lim, Wonsik Yu, Kgj Vishnu, Chanyoung Jeong, Sumanth Chakkirala, Avneesh Singh Verma, Sachin Kashyap, Eg Jeevarathinam, Sunil Kumar Pandey, Jongjae Ryu, Sanjeeb Kumar Ghosh

Institutions: Samsung (India), Samsung Semiconductor (United States), Samsung Electronics (South Korea)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4406895034

FWCI: 2.418

Cites: 7

Cited by: 3

Related to: 10