Work

Design and Benchmark of Iso-Area High Cell Current 5T Asymmetric (5TA) SRAM Cell with Up to 10X Lower Leakage

Year: 2024

Type: conference-paper

Source: IEEE International Conference on Electronics, Circuits and Systems (ICECS)

DOI: 10.1109/icecs61496.2024.10848946

Authors: Ajay Shroti, Anuj Grover

Institution: Indraprastha Institute of Information Technology Delhi

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4406895174

FWCI:

Cites:

Cited by:

Related to: 10