Year: 2025
Type: article
Abstract: Here we present AMD’s 2nd generation 3D V-Cache TM technology and package level results. Key highlights are: 1. Use of face to back (F2B) stacking of 7 nm node cache memory chiplet (SRAM chiplet) on 5 nm node logic chiplet (“Zen 4” compute chiplet). 2. Bond pad via (BPV) landing on top Aluminum pad (AP) instead of top metal layer With the slowdown in Moore’s Law, heterogeneously integrated chiplet architecture enabled by advanced packaging technologies is becoming essential to enabling the continued economically viable growth of power efficient computing. Decreasing interconnect pitches between the various chiplets, beyond what the conventional solder-based packaging techniques offer, is needed to achieve the required power, performance, area, and cost (PPAC) improvements. We demonstrate hybrid bonding (HB) of stacked chiplets at 9 um bond pitches with die to wafer (D2W) stacking to enable an order of magnitude higher bandwidth between chiplets at lower power and latency compared to existing packaging technologies. Moreover, in the top chiplet, the BPV lands on the top AP instead of the M13 top metal layer, enabling shorter connectivity path. Extensive reliability of these parts in an LGA MCM package has been completed, with the units successfully passing suite of package reliability tests.
Source: IMAPSource Proceedings
DOI: 10.4071/001c.129075
Authors: Arsalan Alam, Chandrasekhar Mandalapu, Patrick Cheng, ChihHsiang Tseng, Sean Liu, Liwei Wang, Mihaela Tanasescu, Mahmudur Chowdhury, Aly Garcia, Anadi Srivastava, Sai Vadlamani, Sireesha Gogineni, Tanmay Mudholkar, Jiali ORiain, Yash Kothari, Yong fui Lee, Litao Yang, Anna Yang, Pawan Kulkarni, Aaron Blanchet, Rita Pillman, Bryan Weatherford, Tao Chen, Yolanda Liu, Raja Swaminathan
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
Funder: Advanced Micro Devices
OpenAlex ID: W4406972281