Work

A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth

Year: 2025

Type: article

Abstract: This paper describes the design and implementation of a 4 MHz bandwidth$3{^{\text {rd}}}$-order Discrete-Time (DT) Passive Delta-Sigma Modulator (${\mathrm {P\Delta\Sigma M}}$), which avoids the use of supply voltage-sensitive linear amplifiers. The Switched-Capacitor (SC) operation and amplifier-less nature of its loop filter render the proposed modulator highly supply voltage- and clock frequency-flexible. To explain our design choices, we investigate two key design challenges unique to${\mathrm {P\Delta\Sigma M}}$s. Firstly, the noise criticality of the quantizer ADC due to the lack of (voltage) gain in the loop filter preceding it. Secondly, the inaccessibility of the readily synthesizable and highly frequency-selective loop filter frequency responses typically employed in${\mathrm {\Delta\Sigma M}}$s, caused by the absence of linear amplifiers. We show that the noise-power trade-off of the quantizer ADC in 1 bit P$\Delta \Sigma $Ms is the same as that of the first integrator amplifier in Active${\mathrm {\Delta\Sigma M}}$. Next, we cover the suitability of several passive filters for use in${\mathrm {P\Delta\Sigma M}}$loops. This leads to the selection of the voltage-sampled Charge-Rotating IIR (CR-IIR) filter, for which we show${\mathrm {\Delta\Sigma M}}$-oriented design equations, on which we base the design of our$3{^{\text {rd}}}$-order DT${\mathrm {P\Delta\Sigma M}}$. Measurement results on the resulting prototype${\mathrm {P\Delta\Sigma M}}$, implemented in GlobalFoundries 22 nm FD-SOI CMOS, demonstrate that it achieves a 71.9 dB peak SNDR and 4 MHz bandwidth while consuming 4.4 mW from a 0.9 V supply and occupying 0.076 mm$^{\mathrm {\mathbf {2}}}$of silicon area. The prototype${\mathrm {P\Delta\Sigma M}}$continues to operate at a$2.25\times $reduced supply voltage of 0.4 V, albeit at a reduced bandwidth of 156.25 kHz, where it achieves a peak SNDR of 62 dB while consuming 37.8$\mu $W.

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2025.3536610

Authors: Jeroen Ponte, Harijot Singh Bindra, Bram Nauta

Institution: University of Twente

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Biomedical Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $2,645

Funders: European Commission, European Research Council