Work

Efficient Hardware Accelerator Design for AES Encryption Using High-Level Synthesis Techniques

Year: 2024

Type: conference-paper

Source: International Conference on Integrated Intelligence and Communication Systems (ICIICS)

DOI: 10.1109/iciics63763.2024.10859678

Authors: B.S.S. Tejesh, M. Ramakrishnan

Institution: SRM University

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4407169774

FWCI: 2.485

Cites: 14

Cited by: 8

Related to: 10