Work

Optimisation Study of VLSI Circuit Cell Placement Based on Rectilinear Minimum Steiner Tree and Simulated Annealing Algorithm

Year: 2024

Type: conference-paper

Source: IEEE International Conference on Data Science and Computer Application (ICDSCA)

DOI: 10.1109/icdsca63855.2024.10859623

Authors: Kairen Xue, Zhicheng Wang, Yanpeng Tian, Junlei Xu, Weihong Zhou

Institution: Xi'an University of Technology

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4407214348

FWCI:

Cites: 5

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Related to: 10