Simulation of Vertically Stacked 2-D Nanosheet FETs
Year: 2025
Type: article
Abstract: We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet FET at the ultimate nanosheet thickness, using 2-D materials (2DMs). In particular, our numerical study specifically explores the potential of multilayer vertically stacked GAA MoS2 FETs, considering different geometries and device parameters (e.g., number of stacked nanosheets, spacer dimensions, doping, and so on) with the aim of providing guidelines for obtaining high-performance devices. Sources of nonideality that have been considered are the effects of contact resistance and line-edge roughness (LER), which significantly affect the overall performance of NSFETs. Finally, circuit performance has been benchmarked by calculating the energy per switching and worst case delay of a 32-bit full adder circuit.
Institutions: University of Pisa, TU Wien
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $2,645
OpenAlex ID: W4407214737