Work

Design and Implementation of Sped Technique using Hybrid Adder for Area Reduction

Year: 2024

Type: conference-paper

Source: International Conference on Sustainable Communication Networks and Application (ICSCNA)

DOI: 10.1109/icscna63714.2024.10864064

Authors: Sharmila J, Magesh Kumar S, Sanjay K

Institution: Saveetha University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4407317347

FWCI:

Cites: 9

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Related to: 10