Work

FPGA-Based RISC Processor with Pseudo Open Drain for Power Optimization

Year: 2024

Type: conference-paper

DOI: 10.1109/delcon64804.2024.10866761

Authors: Kiran Sharma, Keshav Kumar, Arnika Patel, Rocky Kumar, Arpita Meet Vaidya, Suraj Singh

Institutions: Parul University, Poornima University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4407361391

FWCI:

Cites: 23

Cited by:

Related to: 10