Work

A Neuron CMOS Type Full Subtractor with Floating Gate Calibration Circuit

Year: 2024

Type: conference-paper

Source: International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

DOI: 10.1109/ispacs62486.2024.10868467

Authors: Hirotaka Furukawa, Hisaya Sawada, Naruaki Hokari, Tatsuya Hasegawa, Daishi Nishiguchi, Fukuhara Masaaki

Institution: Tokai University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Japan Society for the Promotion of Science

Award: A Study on a Low Power Variable Logic Circuit Using Neuron CMOS Inverters

OpenAlex ID: W4407377963

FWCI: 0.806

Cites: 6

Cited by: 1

Related to: 10