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High-Endurance Contention-Aware Power Optimized Hybrid Memory Using Clock Gating Memory

Year: 2024

Type: conference-paper

Source: IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

DOI: 10.1109/edkcon62339.2024.10870768

Authors: Narayana Murty N, Harjit Singh, Sukhmani K. Thethi

Institution: Lovely Professional University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4407466361

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Cites: 27

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Related to: 10