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ASIC Flow Implementation on a 32 Bit RISC V Processor using Cadence

Year: 2024

Type: conference-paper

Source: IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

DOI: 10.1109/edkcon62339.2024.10870604

Authors: Mohammed Abdul Raheem, Mohammed Sabir Hussain, Pathan Rehman Ahmed Khan

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4407467089

FWCI: 0.806

Cites: 3

Cited by: 1

Related to: 10