Work

A Comparative Power & Delay Analysis of Full Adder Designs in 90nm CMOS and 32nm & 5nm CNFET Technologies

Year: 2024

Type: conference-paper

Source: IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

DOI: 10.1109/edkcon62339.2024.10870835

Authors: Aniruddha Sen, Nitish Kumar Sah, Kousik Bhunia, Sumit Saha

Institution: National Institute of Technology Rourkela

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4407474960

FWCI:

Cites: 10

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Related to: 10