Extrinsic and Intrinsic Sources of Temperature‐Dependent Transport Hysteresis in 2D Transistors
Year: 2025
Type: article
Abstract: Hysteresis in charge transport under gate sweep is a common phenomenon in layered two‐dimensional (2D) transistors. Large surface‐to‐volume ratios in 2D layers with numerous hysteresis sources have led to several contradicting experimental observations, particularly in the temperature dependence of total hysteresis, in gated transistors. While this is a major reliability concern for logic devices, controllable hysteresis is a requirement for non‐volatile memory applications, thus necessitating predictive models for device characteristics. Herein, a comprehensive model is developed to account for both the extrinsic (interface and oxide traps) and intrinsic sources of hysteresis with tunable parameters to include device‐specific details. The model reveals that the intrinsic and extrinsic sources in 2D transistors have distinct and contrasting influences on transport hysteresis at different temperatures. The behavior of total transport hysteresis at different temperatures can be used to determine the dominant source of hysteresis in 2D transistors. Using carefully tuned experimental conditions, a bottom‐gated multilayer MoS2 transistor is fabricated and it is experimentally shown that this model can faithfully predict the total transport hysteresis in the device at various temperatures.
Source: physica status solidi (a)
Authors: Rupali Srivastava, Kajal Sharma, Amrita Singh, Srest Somay, Krishna Balasubramanian
Institution: Indian Institute of Technology Delhi
Language: English
Subfield: Materials Chemistry
Field: Materials Science
Domain: Physical Sciences
Open Access status: bronze
Award: G2378097209
OpenAlex ID: W4407591838