Year: 2025
Type: article
Abstract: As the industry moves toward high-performance computing (HPC) for huge data transmission with low power consumption. The requirements for advanced package (PKG) structures have become more challenging. The major engineering requirements for HPC application are high-density, high-speed data transmission, low loss, precision manufacturing with low-cost process. High pin counts need large area package with high mechanical stability and low warpage. The demand for high density and high-speed data transmission becomes strong need for leading edge semiconductor packaging. 2.5D and 3D heterogenous package realize this solution. On the 2.5D heterogenous package structure, high interconnect density with fine line wiring layers providing high speed transmission is required to-connect CPU chips or chiplet arrays and HBM chip stacks. Silicon interposers with through silicon vias (TSVs) have scaled to meet this demand, but face three major barriers: high electrical loss, package size and cost. On the other hand, glass has many properties that make it an ideal core material for advanced substrates such as ultra-low loss tangent, adjustable thermal expansion (CTE), mechanical stability and manufacturability with large panel formats. This paper presents the demonstration of Glass core substrate with fine line redistribution layers (RDL). Glass core substrate with fine pitch metalized through glass vias (TGV) and fabricate RDL with low loss dielectrics. In case of Glass core substrate, three TGV copper metalized processes were compared for process capability, -reliability and high-speed transmission characteristics. Copper metallization provides low resistance, high transmission rate and high-power density. The reliability test results show stable resistance data because of combination of double-sided polymer dielectrics. The double-sided polymer dielectrics providing stress buffer for glass and copper CTE differences. TGVs filled with Cu by three methods were demonstrated with large panel size format max 550x650mm.The ultra-high density RDL process using non-organic protective layer fabricated on the glass substrate. High aspect ratio Cu traces enable to minimum 3um pitch, high transmission rate and high reliability. We also compare high speed transmission characteristics with TGV and transmission trace with multi-layer RDL on panel level format. Finally, we compare the transmission characteristics using eye diagram for heterogenous integration application.
Source: IMAPSource Proceedings
DOI: 10.4071/001c.129747
Institution: Dai Nippon Printing (Japan)
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4407641090