Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum
Year: 2025
Type: conference-paper
Abstract: The development of synchronous circuits currently dominates the semiconductor design industry.However, there are major limiting factors to the synchronous, clocked approach, including the increasing difficulty of clock distribution, increasing clock rates, decreasing feature size, increasing power consumption, timing closure effort, and difficulty with design reuse.Asynchronous (clockless) circuits require less power, generate less noise, produce less electromagnetic interference (EMI), and allow for easier reuse of components, compared to their synchronous counterparts, without compromising performance.As the demand continues for designs with higher performance, higher complexity, and decreased feature size, asynchronous paradigms will become more widely used in the industry, as evidenced by the International Technology Roadmap for Semiconductors' (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues.ITRS predicts that asynchronous circuits will account for 19% of chip area within the next 5 years, and 30% of chip area within the next 10 years.
Source: ASEE Midwest Section Conference
DOI: 10.18260/1-2--51753
Author: Scott C. Smith
Institution: Missouri University of Science and Technology
Language: English
Subfield: Architecture
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4407678260