Detailed Analysis on the Micro-Architecture and Integration of Bit Manipulation Extensions in the SweRV EH1 Core of a RISC-V Processor and its Functional Verification
Year: 2024
Type: conference-paper
Abstract: Embedded system applications and small electronic devices demand cost-effective, high-performance, energy-efficient, and secure processor architectures. In this context, RISC-V has emerged as a significant competitor to conventional architectures like Intel x86 and ARM, particularly in embedded systems and Internet of Things (IoT) applications. The SweRV EH1 core, based on the RISC-V architecture, is specifically designed to meet these demands. In this work, we perform a detailed analysis of the existing SweRV EH1 core microarchitecture and integrate bit manipulation extensions that support low-power embedded applications. The detailed microarchitecture of the SweRV EH1 core is designed and explained, including the bit manipulation extensions. The improved microarchitecture is later tested using Verilator. The results show that the SweRV EH1 core with new bit manipulation extensions improves performance, reduces code density, and enhances power usage efficiency. This contributes to the ongoing research on the RISC-V architecture and provides insights into the benefits of integrating bit manipulation extensions in embedded systems.
Authors: Samina Yasmin, Muhammad Asim Naveed, Tassadaq Hussain, Eduard Ayguade
Institution: Barcelona Supercomputing Center
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4407693434