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Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration

Year: 2025

Type: conference-paper

Abstract: High-Level Synthesis (HLS) enables software engineers to create intricate digital circuit designs using high-level languages like C/C++. While HLS tools can perform functional verification using C/C++ simulation, it is harder to verify that the generated RTL is also correct. This problem is exacerbated for designs which include HLS-generated IPs, such as PCIe or DDR interfaces, or hand-written RTL. While it is possible to perform cycle-accurate verification using C/RTL co-simulation, conventional methods are both slow and typically only focus on unit-level verification which can make it harder to identify the root cause of a bug.

Source: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

DOI: 10.1145/3706628.3708866

Authors: Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi

Institutions: Chinese Academy of Sciences, ShanghaiTech University, Institute of Computing Technology, University of Chinese Academy of Sciences, The University of Sydney

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

OpenAlex ID: W4407953513

FWCI:

Cites: 17

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Related to: 10