Work

A Seven Layer Half-Delay MDSC-MSTOGI-EPLL Based Disturbance Rejection Control With Power Levelling Feature for a SPV Array-Battery System

Year: 2025

Type: article

Source: IEEE Transactions on Industry Applications

DOI: 10.1109/tia.2025.3547289

Authors: Subhadip Chakraborty, Gaurav Modi, Bhim Singh, B. K. Panigrahi

Institution: Indian Institute of Technology Delhi

Language: English

Topic: Microgrid Control and Optimization

Subfield: Control and Systems Engineering

Field: Engineering

Domain: Physical Sciences

SDGs: Affordable and clean energy, Industry, innovation and infrastructure

Open Access status: closed

Funder: Department of Atomic Energy, Government of India

OpenAlex ID: W4408145491

FWCI: 0.392

Cites: 26

Cited by: 1

Related to: 10