Work

Device and Circuit-Level Performance Assessment of Interface Trap Charges on III–V Heterojunction TFETs for Reliability

Year: 2025

Type: article

Source: Journal of Circuits Systems and Computers

DOI: 10.1142/s0218126625502901

Authors: Priyanka Verma, Satyendra Kumar

Institution: Jaypee Institute of Information Technology

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4408200960

FWCI: 0.231

Cites: 46

Cited by: 1

Related to: 10