Verilog HDL-based implementation of UART design
Year: 2025
Type: conference-paper
DOI: 10.1117/12.3060265
Author: Tianjun Zhan
Institution: Xi'an University of Technology
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4408226023
