Work

iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree

Year: 2025

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2025.3549355

Authors: Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Jian Chen, Zhixue He, Xingquan Li

Institutions: South China University of Technology, Chinese University of Hong Kong, Fuzhou University, Peng Cheng Laboratory

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: National Natural Science Foundation of China, Natural Science Foundation of Fujian Province, Natural Science Foundation of Guangdong Province

Awards: G5963008701, G6320596113, G7007863107, G8216305697

OpenAlex ID: W4408235561

FWCI: 0.462

Cites: 29

Cited by: 2

Related to: 10