Thermal Pretreatment of as Cut Wafers for High Efficiency Silicon Heterojunction Solar Cells
Year: 2025
Type: article
Abstract: ABSTRACT Silicon (Si) heterojunction (SHJ) solar cells are today a mature industrial technology allowing the highest efficiency of Si single junction cells. Nevertheless, SHJ efficiency dispersion related to the wafer quality (Si minority carrier lifetime, τ bulk ) can be up to 1% abs with the present specification of high quality n‐type Cz. Thus, in order to enhance the quality of the wafers, several low‐cost annealing processes on as‐cut wafers performed under air atmosphere before entering cell line have been tested. Results suggest that multiple factors are involved in the change of τ bulk . At low temperature (< 500°C), all wafers carrier lifetime improved significantly whereas at high temperature (> 700°C) their quality degrades. In the intermediate temperature range, τ bulk evolution seems to depend on the wafer type (supplier and initial quality), probably due to the combined occurrence of concurrent bulk improvement and contamination mechanisms. Best pre‐annealing conditions of tested as‐cut Cz wafers significantly improve the wafer carrier lifetime and thus the cell efficiency up to +0.8% abs . Nonetheless, further work is needed to foster our comprehension of the mechanisms responsible for the change in τ bulk . Results suggest that behind well‐known POCl 3 gettering route, low temperature gettering mechanisms might be further investigated in order to setup robust process applicable to the wafers of SHJ mass production.
DOI: 10.1002/pip.3906
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4408310351