An SDPF RISC‐V Processor With 55.9% Dhrystone Improvement Using Two‐Stage Pseudo‐Pipelined Architecture for IoT Applications
Year: 2025
Type: article
DOI: 10.1002/cta.4514
Institution: Sun Yat-sen University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
Award: G137698199
OpenAlex ID: W4408330015