Work

Localization of a Robot on FPGA with 5-Stage Pipeline RISC-V CPU

Year: 2025

Type: article

Source: INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT

DOI: 10.55041/ijsrem42440

Authors: Dr. K S Geetha, Deepika M, Mrudhul M J, S Vedram

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4408450480

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