OpenAlex | A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection

A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection

Work

Year: 2025

Type: article

Source: Microelectronics Journal

Authors Zhaoyang Liu, Zhanhao Wen, Bao Chen, Jiang Xu, Zedong Wang +1 more

Cites: 43

Cited by:

Related to: 10

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Citation percentile (by year/subfield):

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Sustainable Development Goal Affordable and clean energy

Open Access status: closed