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Performance Analysis of Different Optimized Digital Parallel Adders

Year: 2024

Type: conference-paper

Source: IEEE Global Conference for Advancement in Technology (GCAT)

DOI: 10.1109/gcat62922.2024.10924060

Authors: Venu M G, Dileep B N, Raghavendra H, Veena M B

Institution: B.M.S. College of Engineering

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4408717207

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Cites: 10

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Related to: 10